(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a MOS transistor.
(b) Description of the Related Art
Recently, technologies for MOS devices have been rapidly developed, so that small-sized high-performance MOS devices can be obtained. In order to achieve the small-sized high-performance MOS devices, technologies relating to thicknesses of gate oxide layers, source/drain regions, and channel region must be improved.
As the MOS transistors are highly integrated, a short channel effect (SCE) occurs. In order to suppress the short channel effect, the thickness of the gate oxide layer needs to be small. In addition, the source/drain regions need to be formed with a shallow junction to reduce a charge sharing effect.
In addition, in order to suppress the short channel effect of the MOS transistor, a lightly doped drain region and a halo region may be provided in a vicinity of the channel region. Preferably, impurity ions implanted to adjust threshold voltages are distributed on or near a surface of the channel region.
On the other hand, boron (B) or BF ions are used to adjust the threshold voltage in n-channel MOS transistors and form the LDD region in p-channel MOS transistors.
However, B ions have a tendency to be widely diffused as subsequent processes such as thermal treatment are carried out. As a result, in the p-channel MOS transistor, B ions may be sufficiently diffused to reach an EOR (end of range) of the channel region, so that a parasitic capacitance between the gate and the drain may increase. On the other hand, in the n-channel MOS transistor, B ions may be sufficiently diffused into a lower portion of the substrate to reach a lower portion of the channel region, so that it is difficult to suppress the short channel effect.